1. Field of the Invention
The present invention relates to synchronous semiconductor memory devices, and more particularly to a synchronous semiconductor memory device that receives a plurality of external control signals in synchronization with a clock signal, and makes transition among a plurality of operating states in response to the captured external control signals.
2. Description of the Background Art
Semiconductor memory devices are classified into two types: synchronous semiconductor memory devices that operate in synchronization with a clock signal, and asynchoronous semiconductor memory devices. For example, an asynchronous dynamic random access memory (DRAM) asynchronously captures external control signals, such as a raw address strobe (RAS) signal, a column address strobe (CAS) signal, and a write enable (WE) signal, as commands indicating operating modes. A control signal generator included in the DRAM uses an asynchronous S-R flip-flop circuit, a delay circuit, or the like, to generate various kinds of internal control signals according to the commands captured. The internal control signals enable reading data from and writing data to a memory cell array. They include, for example, a row address latch (RAL) signal to latch a row address signal to a row address buffer, a row address enable (RADE) signal to activate a row decoder, a word line enable (WLE) signal to activate a word line driver, a column address latch (CAL) signal to latch a column address signal to a column address buffer, and a column decoder enable (CDE) signal to activate a column decoder.
When RAS signal is activated, RAL signal is activated. With an edge of this RAL signal as a trigger, row-related internal control signals, e.g., RADE and WLE signals, are activated successively. When RAS signal is inactivated, WLE signal is inactivated. With the edge of this WLE signal as a trigger, the row-related internal control signals are inactivated successively.
A synchronous dynamic random access memory (SDRAM) receives external control signals including RAS signal, CAS signal and WE signal, in synchronization with a clock signal. The internal control signals, such as RAL signal, RADE signal and WLE signal, are generated successively, basically in the same manner as in the above asynchronous DRAM.
As explained above, in a conventional control signal generator, the internal control signals are generated successively. This requires a complicated circuit to accurately adjust rising and falling timings of the internal control signals. Therefore, in order to design DRAMs with different memory cell array arrangements, as well as in order to design DRAMs with different operating modes, the configuration of the control signal generators had to be changed extensively. As a result, a considerable time was required to design various kinds of DRAMs.